The invention relates generally to methods and devices for providing simultaneously switched outputs for communication over a bus, and more particularly to devices and methods for reducing switching noise during simultaneous switching of the outputs from one logic level to another.
Communicating data, such as command information, video data, audio data and any other suitable information, over a bus, such as a plurality of data links, among the plurality of circuits can be done in many ways. Fast interfaces are sometimes used between differing circuits, such as between different chips (using for example double data rate interfaces). A main problem with fast interfaces results from the fast interface using simultaneously switched outputs (SSO). Data is communicated over a bus in parallel fashion between differing circuits. Where the fast interfaces use simultaneously switched outputs, a large power and ground bounce can occur during simultaneous switching of many outputs from a logic level xe2x80x9c0xe2x80x9d to a logic level xe2x80x9c1xe2x80x9d (or from a logic xe2x80x9c1xe2x80x9d to a logic xe2x80x9c0xe2x80x9d). As a result, glitches, noise, signal skewing, clock skewing and other interface problems can occur.
For example, as shown in FIG. 1, a data transmitter 10 may communicate data over data links 12 (e.g., a bus) using a fast interface, such as an I/O buffer interface 14. A data provider 16, such as a bus controller or any other suitable circuit, provides output of data in parallel over a bus 18 through simultaneous switching outputs as known in the art. The I/O buffer interface 14 also includes simultaneous switching outputs. A receiving circuit 20, such as another chip or any other suitable receiving circuit, includes a corresponding I/O buffer interface 22 that receives the communicated data over the data links 12. The data is then transferred to a data receiving circuit 24, such as a bus controller, or any other suitable device. Bidirectional data transfer is typically provided, although not shown. The I/O buffer interface 14 utilizes simultaneous switching outputs; the data links 12 may each include data at a logical xe2x80x9c1xe2x80x9d level and subsequently on the next cycle include data at the xe2x80x9c0xe2x80x9d level. The switching of all the data lines from one logic level to another or a subset of data lines from one logic level to another, can result in undesirable noise, glitches, signal skewing, and clock skewing.
Several suggested solutions include using a chip package with lower parasitic inductance, or decreasing output signal slew rates. However, small output signal slew rates typically decrease the working frequency of the chip making the chip unnecessarily slower than needed. In addition, low impedance circuits may still have simultaneously switched output problems at a higher working frequency.
Accordingly, there exists a need for a method and apparatus for simultaneously communicating information over a plurality of data links that reduces noise and other problems typically associated with simultaneously switched outputs.